The present invention relates to a substrate for an electrooptical device, and, more particularly, to a substrate for an electrooptical device appropriate for use in a reflective electrooptical device.
A xe2x80x9clight valvexe2x80x9d in this description represents a transmissive light modulator element or a light-reflective light modulator element
The applicant of this application has disclosed a substrate for a liquid-crystal display panel, the liquid-crystal display panel, and a projection display apparatus, to be discussed below, in Japanese Patent Application 8-279388 filed Oct. 22, 1996.
Referring to FIG. 18, a projection display apparatus (a liquid-crystal display projector) using a reflective liquid-crystal display panel as a light valve includes, in a system optical axis L0, a polarizing illumination device 1100 mainly composed of a light source unit 1110, an integrator lens 1120, and a polarizer element 1130, a polarizing beam splitter 1200 which reflects an S-polarized light exiting from the polarizing illumination device 1100 from an S-polarized light reflecting surface 1201, a dichroic mirror 1412 which separates a blue light (B) component from the light beam reflected from the S-polarized light reflecting surface 1201 of the polarized light beam splitter 1200, a reflective liquid-crystal display light valve 1300B for modulating the separated blue light (B), a dichroic mirror 1413 for reflecting a red light (R) component of the light from which the blue light has been separated through the dichroic mirror 1412, a reflective liquid-crystal display light valve 1300R for modulating the separated red light (R), a reflective liquid-crystal display light valve 1300G for modulating the remaining green light (G) transmitted through the dichroic mirror 1413, and a projection optical system 1500 including a projection lens. Light beams modulated through the three reflective liquid-crystal display light valves 1300R, 1300G, and 1300B are directed in the opposite directions along the respective optical paths thereof, and are synthesized through the dichroic mirrors 1413 and 1412 and the polarizing beam splitter 1200. The synthesized light beam is then projected to a screen 1600 through the projection optical system 1500. A liquid-crystal display panel 530 shown in a cross-sectional view in FIG. 19 is used for each of the reflective liquid-crystal display light valves 1300R, 1300G, and 1300B.
The liquid-crystal display panel 530 includes a reflective liquid-crystal display panel substrate 531 which is affixed using an adhesive agent to a support substrate 532 made of glass or ceramic, a glass substrate (opposing substrate) 535 on a light incident side of the panel 530 having thereon an opposing electrode (common electrode) 533 made of a transparent electrically conductive film (ITO), separated from the reflective liquid-crystal display panel substrate 531 by a sealing material 536 that extends on and along the outline of the reflective liquid-crystal display panel substrate 531, and a known TN (Twisted Nematic) type liquid crystal 537 or an SH (Super Homeotropic) type liquid crystal 537 containing liquid-crystal molecules in a homeotropic alignment with no voltage applied, encapsulated in the space enclosed by the reflective liquid-crystal display panel substrate 531, the glass substrate 535, and the sealing material 536.
FIG. 20 shows a major circuit arrangement of the reflective liquid-crystal display panel substrate 531 used in the liquid-crystal display panel 530, and FIG. 21 is an enlarged plan view showing the layout of the reflective liquid-crystal display panel substrate 531. The reflective liquid-crystal display panel substrate 531 includes a rectangular pixel area (a display area) 520 in which a matrix of many pixel electrodes 514 shown in FIG. 19 is arranged, scanning line drive circuits (Y drivers) 522 (522R and 522L), arranged on the left- and right-hand sides of the pixel area 520 and composed of a shift register and a buffer circuit for scanning gate lines (scanning electrodes or row electrodes) Y0-Yn, a precharge and test circuit 523 arranged on and outside the top side of the pixel area 520 working for data lines (source lines, signal electrodes, or column electrodes) X0-Xm an image signal sampling circuit 524, arranged below the pixel area 520, for sampling an image signal in accordance with image data to feed the image signal to the data line X0-Xm, an outline seal area 527 where the above-referenced sealing material 537 is positioned outside the scanning line drive circuit 522, the precharge and test circuit 523, and the image signal sampling circuit 524, a plurality of terminal pads 526 which are rigidly attached to a flexible tape wiring 539 through an anisotropic electrically conductive film (ACF) 538, a shift register 521 arranged between a row of the terminal pads 526 and the seal area 527 for generating a selection pulse for the image signal sampling circuit 524, and relay terminal pads (so-called silver-point pads) 529R and 529L arranged on both sides of the shift register 521 for feeding power to the opposing electrode 533 on the glass substrate 535.
The shift register 521 and the image signal sampling circuit 524 form a signal line drive circuit (X driver) 540 for driving the data lines X0-Xm. The signal line drive circuit 540 employs a point-at-a-time scanning method in which the signal line drive circuit 540 successively feeds a data signal to the data lines X0-Xm one by one. The signal line drive circuit 540 may employ a line-at-a-time scanning method in which a data signal is concurrently fed to all data lines X0-Xm. The pixel area 520, in which a matrix of pixels (pixel electrodes 514) is arranged, has the data lines X0-Xm. and the gate lines Y0-Yn, arranged in a grid, and pixel selecting MOSFETs (insulated-gate field-effect transistors) T (T00-Tnm) respectively arranged in intersections of the data lines and the gate lines. The source S of the transistor T of each pixel is connected to the data line X, and the gate G thereof is connected to the gate line, and the drain D thereof is connected to the pixel electrode 514 and storage capacitor C, as will be discussed later. The pixel electrode 514 of the reflective liquid-crystal display panel substrate 531 is connected to a liquid-crystal cell LC of the liquid crystal 537 encapsulated between the reflective liquid-crystal display panel substrate 531 and the glass substrate 535 as the opposing substrate.
A light shielding film 525 (see FIG. 19) is arranged at the same level as the pixel electrode 514, as a top layer, to prevent light from entering peripheral circuits (the scanning line drive circuits 522R and 522L, the precharge and test circuit 523, and the image signal sampling circuit 524) arranged inside the seal area 527.
FIG. 22 is an enlarged plan view partly showing the pixel area 520 of the reflective liquid-crystal display panel substrate 531, and FIG. 23 is a cross-sectional view of the pixel area 520 taken along line Axe2x80x94Axe2x80x2 in FIG. 22. Referring to FIG. 23, designated 501 is a monocrystal P semiconductor substrate (an N semiconductor substrate is optional), and having a size as large as 20 mm by 20 mm, for instance. A P-type well region 502 is formed on the surface (major surface) of an element forming region (for a MOSFET, for instance) of the semiconductor substrate 501, and a field oxidation film (so-called LOCOS) 503 is formed to isolate elements in a non-element forming region of the semiconductor substrate 501. Referring to FIG. 23, the P-type well region 502 is formed as a common well region for the pixel area 520 where a matrix of a number of pixels, for instance, as many as 768xc3x971024, is arranged in a matrix configuration and is separated from the P-type well region into which the elements for the peripheral circuits, outside the pixel area 520, (including the scanning line drive circuits 522R and 522L, the precharge and test circuit 523, the image signal sampling circuit 524, and the signal line drive circuit 521) are embedded.
Two openings are formed in the field oxidation film 503 in the segment region of each pixel. Formed in one opening is a pixel selecting N channel MOSFET (a gate-insulated field-effect transistor) T which is composed of a gate electrode 504a of polysilicon or metal silicide, formed on a gate insulating layer 504b in the center thereof, and an N+source region 505a and an N+drain region 505b, arranged on both sides of the gate electrode 504a on the surface of the P-type well region 502. The gate electrodes 504a of a plurality of pixels arranged in a row extend in the direction of rows of the pixels to form the gate line 504 (Y in FIG. 20).
A P capacitor electrode region 508, common to the direction of rows, is formed in the other opening on the P-type well region 502, and a capacitor electrode 509a of polysilicon or metal silicide is formed on the P capacitor electrode region 508 with an insulator film (a dielectric film) 509b interposed therebetween. The P capacitor electrode region 508 and the capacitor electrode 509a form a storage capacitor C that holds a signal selected by the pixel selecting transistor T.
A first interlayer insulator film 506 is deposited on the gate electrode 504a and the capacitor electrode 509a, and a first aluminum-based metal layer is deposited on the interlayer insulator film 506.
Included in the first metal layer are the data line 520 (X shown in FIG. 20) extending in the direction of columns, a source electrode wiring 506a electrically connected to the source region 504b through a contact hole 506a which is projected from the data line 507 in a comblike fashion, and a relay wiring 510 electrically connected to the drain region 505b via a contact hole 506b and electrically connected to the capacitor electrode 59a via a contact hole 506c. 
A second interlayer insulator film 511 is formed on the first metal layer formed of the data line 507, the source electrode wiring 506a, and the relay wiring 510, and a second aluminum-based metal layer is deposited on the second interlayer insulator film 511. Included in the second metal layer is a light shielding film 512 for partly covering the pixel area 520. The second metal layer forming the light shielding film 512 serves as an interconnect wiring between elements in the peripheral circuits surrounding the pixel area 520 (including the scanning line drive circuits 522R and 522L, the precharge and test circuit 523, the image signal sampling circuit 524, and the signal line drive circuit 521).
A plug accommodating opening 512a is arranged in the light shielding film 512 in the position correspondingly above the relay wiring 510. A third interlayer insulator film 513 is formed on the light shielding film 512, and a rectangular pixel electrode 514 as a reflective electrode, generally corresponding to a single pixel is formed on the third insulator film 513. A contact hole 516 is arranged to pierce the third interlayer insulator film 513 and the second interlayer insulator film 511 correspondingly in the opening 512a of the light shielding film 512. After a refractory metal such as tungsten is embedded in the contact hole 516 using a CVD technique, the refractory metal deposited on the third insulator film 513 and the surface of the third insulator film 513 are polished using a CMP (chemical-mechanical polishing) to a mirror-grade flatness. In succession, an aluminum layer is deposited using a low-temperature sputtering technique, and is patterned to form a rectangular pixel electrode (reflective electrode) 514 having one side as long as 15 to 20 mm. The relay wiring 510 and the pixel electrode 514 thereabove are electrically connected through a columnlike interconnect plug (interlayer conductor) 515. A passivation layer 517 is generally deposited over the pixel electrodes 514.
In a method available for producing the interconnect plug 515, after flattening the third insulator film 513 using the CMP technique, a contact hole is drilled, and a refractory metal, such as tungsten, is embedded thereinto.
In a method of driving the reflective liquid-crystal display panel substrate 531 thus constructed, the scanning line drive circuit 522 selects the gate line Y0, and during a pixel selective period (a horizontal period), the signal line drive circuit 540 successively applies the data signal to the data lines X0-Xm one by one for each pixel selective period (column selective period), and the data signal is written onto the liquid-crystal cell LC connected to the storage capacitor C and the pixel electrode 514 in each pixel in a first column in a point-at-a-time scanning method.
For a selective period during which the scanning line drive circuit 522 selects the gate line Y1, the data signal is written to the liquid-crystal cell LC connected to the storage capacitor C and the pixel electrode 514 in each of the pixels in a second row in a point-at-a-time scanning method. When the writing of the data signal is performed on the pixels on an (n+1)-th row in this way, the write period for all pixels (the transfer of one frame of the image signal in the signal line drive circuit 540) ends, and after all pixel display period, the transfer of the next frame starts over.
When the transfer of the next frame starts over, the data signal in the first row and the first column is refreshed (rewritten) during the selective period of the gate line Y0, but the remaining pixels on the first row and the pixels on the second and subsequent rows maintain the signal of the prior frame. The switching between the image of the prior frame and the image of the subsequent frame successively takes place at the pixels in a point-at-a-time scanning method with both images concurrently presented on screen, thereby causing non-uniformity in the display screen.
When the number of pixels is relatively small, the write period is reduced, and the non-uniformity in the display screen is not so serious. As the number of pixels increases, the write time for all pixels becomes long, and the display time for all pixels becomes relatively short, and the non-uniformity of the display screen is pronounced, thereby degrading the image quality. The signal line drive circuit 540 may employ the line-at-a-time scanning method rather than the point-at-a-time scanning method. In such a case, however, during the write time for all pixels, the switching between the image of the prior frame and the image of the subsequent frame proceeds in a line-at-a-time scanning method, and is presented on the display screen. Non-uniformity in the display screen also results. When the number of pixels increases, the non-uniformity in the display screen leads to a degradation in the image quality. For this reason, the attempt to increase the size and definition of the display screen with a high number of pixels has been subject to a limitation.
In view of the above problem, a first object of the present invention is to provide a substrate for an electrooptical device which presents a high-quality image free from an image non-uniformity on the display screen with the sequence of writing not pronounced on the display screen regardless of whether a point-at-a-time writing method or a line-at-a-time writing method is in use.
It is a second object of the present to provide a substrate for an electrooptical device which is appropriate for use in a digitally driven display device such as a liquid crystal (LC), DMD, FED, PDP, EL, or LED.
A substrate for an electrooptical device of the present invention includes a signal electrode, a first sample-and-hold circuit electrically coupled to the signal electrode, a second sample-and-hold circuit electrically coupled to the signal electrode, a pixel drive circuit, and a pixel electrode electrically coupled to the pixel drive circuit, wherein, when a signal of an (N+1)-th image is applied to the signal electrode, the pixel drive circuit applies a voltage to the pixel electrode during a first duration of time in response to a signal of an N-th image stored in the first sample-and-hold circuit, and the second sample-and-hold circuit stores a signal of the (N+1)-th image within the first duration of time, and when a signal of an (N+2)-th image is applied to the signal electrode, the pixel drive circuit applies a voltage to the pixel electrode during a second duration of time in response to the signal of the (N+1)-th image stored in the second sample-and-hold circuit, and the first sample-and-hold circuit stores the signal of the (N+2)-th image within the second duration of time, and wherein N is a natural number. The present invention thus achieves the above objects.
Preferably, the substrate for an electrooptical device further includes a first scanning electrode to which a first write timing signal is applied, and a second scanning electrode to which a second write timing signal is applied, wherein the first sample-and-hold circuit includes a first signal hold circuit, and a first signal writing circuit electrically coupled to the first scanning electrode, the second sample-and-hold circuit includes a second signal hold circuit, and a second signal writing circuit electrically coupled to the second scanning electrode. The first signal writing circuit electrically connects the signal electrode to the first signal hold circuit in response to the first write timing signal, and the second signal writing circuit electrically connects the signal electrode to the second signal hold circuit in response to the second write timing signal.
In one embodiment, the first signal writing circuit is a first transistor, and the second signal writing circuit is a second transistor having the same semiconductor type as that of the first transistor.
In one embodiment, the first signal writing circuit is a first transistor, and the second signal writing circuit is a second transistor having a semiconductor type complementary to that of the first transistor.
Preferably, the substrate for an electrooptical device further includes a scanning electrode drive circuit for outputting a scanning electrode drive wave, and a write timing circuit for receiving a scanning electrode drive wave and a timing signal that alternates in level every frame period, wherein, in response to the scanning electrode drive wave and the timing signal, the write timing circuit applies the first write timing signal to the first scanning electrode during an odd frame period and applies the second write timing signal to the second scanning electrode during an even frame period.
In one embodiment, the substrate for an electrooptical device further includes an odd-frame scanning electrode drive circuit for applying the first write timing signal to the first scanning electrode during an odd frame period, and an even-frame scanning electrode drive circuit for applying the second write timing signal to the second scanning electrode during an even frame period.
Preferably, the pixel drive circuit includes a first signal reading circuit, a second signal reading circuit, and a common pixel drive circuit, wherein the first signal reading circuit electrically connects the first sample-and-hold circuit to the common pixel drive circuit in response to a first read timing signal, the second signal reading circuit electrically connects the second signal hold circuit to the common pixel drive circuit in response to a second read timing signal, and the common pixel drive circuit drives a pixel in response to the signal from one of the first reading circuit and the second reading circuit.
In one embodiment, the first reading circuit is a third transistor, and the first reading circuit is a fourth transistor having the same semiconductor type as that of the third transistor.
Preferably, the first reading circuit is a third transistor, the first reading circuit is a fourth transistor having a semiconductor type complementary to that of the third transistor, and the first read timing signal and the second read timing signal are the same signal.
In one embodiment, the common electrode drive circuit is a fifth transistor, one terminal of the fifth transistor is electrically connected to a pixel drive power source, and the other terminal of the fifth transistor is electrically connected to the pixel electrode.
In another embodiment, the common electrode drive circuit is a fifth transistor, one terminal of the fifth transistor is electrically connected to a pixel drive power source, and the other terminal of the fifth transistor is electrically connected to the pixel electrode.
In yet another embodiment, the pixel drive circuit includes a first pixel drive circuit, and a second pixel drive circuit, wherein the first pixel drive circuit electrically connects the first sample-and-hold circuit to the pixel electrode in response to the first read timing signal, and the second pixel drive circuit electrically connects the second sample-and-hold circuit to the pixel electrode in response to the second read timing signal.
In yet another embodiment, the first pixel drive circuit is a third transistor, and the second pixel drive circuit is a fourth transistor having the same semiconductor type as that of the third transistor.
Preferably, the substrate for an electrooptical device further includes a read timing circuit, wherein the read timing circuit outputs the first read timing signal during an odd frame period and outputs the second read timing signal during an even frame period, in response to a timing signal, the level of which alternates every frame period.
In one embodiment, the read timing circuit interposes a blanking period between the first read timing signal and the second read timing signal.
In yet another embodiment, the first pixel drive circuit is a third transistor, and the second pixel, drive circuit is a fourth transistor having a semiconductor type complementary to that of the third transistor.
Preferably, the timing signal, which alternates in level every frame period, is used as the first read timing signal during the odd frame and is used as the second read timing signal during the even frame.
In one embodiment, a signal applied to the signal electrode is an analog signal.
In yet another embodiment, a signal applied to the signal electrode is a pulse-width modulated signal.
In yet another embodiment, the electrooptical device of the present invention includes the substrate for the electrooptical device, a light-transmissive substrate opposing the substrate for the electrooptical device, and an electrooptical material interposed between the substrate for the electrooptical device and the light-transmissive substrate.
In yet another embodiment, an opposing electrode is mounted on the light-transmissive substrate, and a common voltage, which alternates every frame period, is applied to the opposing electrode.
In yet another embodiment, electronic equipment of the present invention includes the electrooptical device, as a display unit.
In yet another embodiment, a projection display apparatus of the present invention includes the electrooptical device as a light modulator unit.
A substrate for an electrooptical device of the present invention includes a plurality of pixel electrodes arranged in a matrix configuration and a plurality of storage circuits respectively electrically coupled to the plurality of the pixel electrodes, wherein each of the plurality of the storage circuits includes a first latch circuit, and a second latch circuit, wherein the first latch circuit is electrically coupled to at least one first scanning line and a signal electrode, and he second latch circuit is electrically coupled to at least one second scanning line, the first latch circuit, and the pixel electrode. When the first latch circuit is supplied with a first timing signal through at least one first scanning line, the first latch circuit stores a data signal applied to the signal electrode until a next first timing signal is applied. When the second latch circuit is supplied with a second timing signal through at least one second scanning line, the second latch circuit receives the data signal stored in the first latch circuit, and feeds the data signal to the pixel electrode until a next second timing signal is applied. The first timing signal is successively applied to all first latch circuits in a row in the matrix configuration, and the second timing signal is concurrently applied to all second latch circuits each time the first timing signal is applied to all first latch circuits in the row. The present invention thus achieves the above objects.
A substrate for an electrooptical device of the present invention having a pixel electrode for a pixel at each of intersections of scanning electrodes and signal electrodes arranged in a matrix configuration, includes digital storage means, which includes a plurality of cascaded storage cells, and is arranged for each pixel to drive the pixel in accordance with the storage output from the last stage of the storage cells, wherein the digital storage means temporarily stores digital data coming in to the signal electrode in the plurality of the cascaded storage cells while shifting the stored data along the cascaded storage cells thereof. The present invention thus achieves the above objects.
Preferably, the first latch circuit includes a first data selecting element for capturing the data signal, and a first flipflop for storing the data signal captured through the first data selecting element, and the second latch circuit includes a second data selecting element for capturing the data signal stored in the first flipflop, and a second flipflop for storing the data signal captured through the second data selecting element, wherein an output terminal of the second flipflop is electrically connected to the pixel electrode.
Preferably, the first data selecting element is a first transistor for electrically connecting the data signal line to the first flipflop in synchronization with the first timing signal, the first flipflop is a first synchronization flipflop which performs a storage operation in synchronization with the first timing signal, the second data selecting element is a second transistor for electrically connecting the first flipflop to the second flipflop in synchronization with the second timing signal, and the second flipflop is a second synchronization flipflop which performs a storage operation in synchronization with the second timing signal.
In one embodiment, the first data selecting element is a first one-input gating element which performs a logic operation in synchronization with the first timing signal, the first flipflop is a first synchronization flipflop which performs a storage operation in synchronization with the first timing signal, the second data selecting element is a second one-input gating element which performs a logic operation in synchronization with the second timing signal, and the second flipflop is a second synchronization flipflop which performs a storage operation in synchronization with the second timing signal.
In yet another embodiment, at least one of the first one-input gating element and the second one-input gating element is a clocked inverter.
In yet another embodiment, at least one of the first one-input gating element and the second one-input gating element is a three-state buffer.
Preferably, the first synchronization flipflop includes a first even-numbered inverter circuit including an even number of inverters connected in a cascade configuration, and a first storage control transistor for disconnecting an electrical connection between the input of an initial-stage inverter and the output of a feedback inverter in the first even-numbered inverter circuit in synchronization with the first timing signal, the second synchronization flipflop includes a second even-numbered inverter circuit including an even number of inverters connected in a cascade configuration, and a second storage control transistor for disconnecting an electrical connection between the input of an initial-stage inverter and the output of a feedback inverter in the second even-numbered inverter circuit in synchronization with the second timing signal.
In one embodiment, the first synchronization flipflop includes a first even-numbered inverter circuit including an even number of inverters connected in a cascade configuration, a feedback stage inverter in the first even-numbered inverter circuit is a first clocked inverter which suspends a logic operation in synchronization with the first timing signal, the second synchronization flipflop includes a second even-numbered inverter circuit including an even number of inverters connected in a cascade configuration, and a feedback-stage inverter in the second even-numbered inverter circuit is a first clocked inverter which suspends a logic operation in synchronization with the first timing signal.
Preferably, at least one of the first even-numbered inverter circuit and the second even-numbered inverter circuit is a double inverter circuit having two inverters.
Preferably, the substrate for an electrooptical device further includes a serial-to-parallel converting shift register for applying the digital data to the signal electrode, a scanning electrode selecting shift register for successively selecting the scanning electrodes, a latch timing circuit for generating the first timing signal in accordance with a scanning electrode drive wave from the scanning electrode selecting shift register.
In one embodiment, an electrooptical device of the present invention includes the substrate for the electrooptical device, a light-transmissive substrate opposing the substrate for the electrooptical device, and an electrooptical material interposed between the substrate for the electrooptical device and the light-transmissive substrate.
In yet another embodiment, an opposing electrode is mounted on the light-transmissive substrate, and a common voltage, which alternates every frame period, is applied to the opposing electrode.
In yet another embodiment, electronic equipment includes the electrooptical device, as a display unit.
In still yet another embodiment, a projection display apparatus of the present invention includes the electrooptical device, as a light modulator unit.
A substrate for an electrooptical device of the present invention includes a plurality of pixel electrodes arranged in a matrix configuration, and a plurality of active element circuits respectively electrically coupled to the plurality of the pixel electrodes, wherein each of the plurality of active element circuits performs concurrently in parallel both a pixel drive operation for reading a temporarily stored prior signal to drive a pixel, and a temporary storage operation for storing a subsequent signal for the same pixel which occurs in the signal electrode after a predetermined duration of time from the prior signal. The present invention thus achieves the above object.
To resolve the above problem, the present invention provides means in an electrooptical device having a pixel electrode of a pixel at each of intersections of the scanning electrodes and the signal electrodes arranged in a matrix configuration, wherein each pixel includes an embedded active element circuit which performs concurrently in parallel both a pixel drive operation for reading a temporarily stored prior signal (a signal of a prior frame, for instance) to drive a pixel, and a temporary storage operation for storing a subsequent signal (a signal of a subsequent frame, for example) for the same pixel which occurs in the signal electrode after a predetermined duration from the prior signal.
In conventional active element circuits, the timing of temporarily storing a signal in a storage capacitor in the same pixel and the timing of pixel driving the electrooptical material coincide with each other. In accordance with the electrooptical device of the present invention, the timing of temporarily storing the signal from the signal electrode and the timing of reading the temporarily stored signal to drive the pixel are positively shifted within a constant duration (one frame period, for instance), all pixels are concurrently driven for a next period (for a concurrent still image presentation). The constant duration is not limited to a full frame period, and when one full frame successively includes R, G, and B subframes in a color-sequential display method (a field color successive presentation method), the subframe is also treated as a constant duration.
Regardless of the point-at-a-time scanning method and the line-at-a-time scanning method, the write sequence is merely a temporary storage sequence in the present invention. The write sequence is not pronounced as a pixel drive sequence, and frame switching is performed at a time on all pixels. For this reason, the non-uniformity on the display screen is eliminated, and a substrate for an electrooptical device having a high image quality is provided. A large-size display screen or high-definition display screen results regardless of the number of pixels. Concurrent driving of all pixels (concurrent still image presentation) is performed for a constant duration (one frame period, for instance). Since the display time and the write time are not exclusive to each other, the display time is allowed to be longer than that in the conventional art. A higher definition display is thus provided. The temporary storage operation for all pixels for the constant duration (one frame period, for instance) is achieved, permitting longer write time. With a slow signal transfer speed, the peripheral circuits are simplified in construction or modified to accommodate a higher number of pixels. A frame memory for display data attached external to the electrooptical device substrate is dispensed with.
The delayed pixel drive type active element circuit includes a plurality of sample-and-hold means that performs the temporary storage operation exclusively or successively in a time division manner to capture a signal from a signal electrode, and pixel drive means that performs the pixel drive operation exclusively or successively in a time division manner by reading the temporarily stored signal from the sample-and-hold means. It is generally sufficient if the sample-and-hold means is constructed of first and second sample-and-hold means. In such a case, the write duration of the subsequent signal and the pixel drive duration for the prior signal coincide with each other. The use of third sample-and-hold means is optional. When N sample-and-hold means are used, the write duration of the subsequent signal is set to be (Nxe2x88x921) times the pixel drive duration for the prior signal. The effect of the simplification of the peripheral circuits and the use of a high number of pixels are substantial as a result of a slow signal transfer speed. When three sample-and-hold means are used in the color sequential display method, a B subframe signal may be written throughout the pixel drive period for an R subframe and the pixel drive period for a G subframe.
Focusing on the signal of the sample-and-hold means, a serial signal on a signal electrode line is serial-to-parallel converted into a prior signal and a subsequent signal through the sample-and-hold means when a single line of signal electrodes is assigned to pixels, and the prior signal and the subsequent signal are then temporarily stored therein. In such a case, the required number of scanning electrodes for controlling the selection timing of a plurality of sample-and-hold means becomes equal to the number of the sample-and-hold means. For instance, when there are first and second sample-and-hold means, a single line of signal electrode and two lines of scanning electrodes are needed. Conversely, when there are a signal line dedicated to an odd frame and a signal line dedicated to an even frame, a single scanning line is shared, and the first and second sample-and-hold means perform a temporary storage function rather than functioning as a serial-to-parallel converter means.
The first sample-and-hold means includes first signal hold means and first signal writing means for sampling a signal on the signal electrode into the first signal hold means by on and off operations in response to a first selection timing signal. The second sample-and-hold means includes second signal hold means and second signal writing means for sampling a signal on the signal electrode into the second signal hold means by on and off operations in response to a second selection timing signal. The prior signal (a signal of a prior (odd) frame, for instance) is temporarily held in the first signal hold means by the first signal writing means, while the subsequent signal (a signal of a subsequent (even) frame, for instance) is temporarily held in the second signal hold means by the second signal writing means.
Specifically, the first signal writing means is a first transistor with one terminal thereof electrically connected to the signal electrode and with the other terminal thereof electrically connected to the first signal hold means. The second signal writing means is a second transistor having the same semiconductor type as that of the first transistor, with one terminal electrically connected to the signal electrode and with the other terminal electrically connected to the second signal writing means. The transistors are not limited to unipolar transistors. Bipolar transistors may also be used. The use of the first and second transistors of the same semiconductor type controls differences in element characteristics, thereby providing advantages in analog driving.
In contrast, the first signal writing means may be a first transistor with one terminal thereof electrically connected to the signal electrode and with the other terminal thereof electrically connected to the first signal hold means. The second signal writing means may be a second transistor having a semiconductor type complementary to that of the first transistor, with one terminal electrically connected to the signal electrode and with the other terminal electrically connected to the second signal writing means. The two transistors are thus complementary to each other in polarity.
With these first and second sampling means incorporated in the active element circuit, write timing means is required in the peripheral circuits to feed the first write timing signal and the second write timing signal to the active element circuit. As the write timing means, a timing signal such as an AC signal alternating at every frame period may be used. Specifically, in response to the timing signal of the scanning electrode drive wave from the scanning electrode drive means, the write timing means generates the first write timing signal during-the odd frame period and the second write timing signal during the even frame period. The write timing means may be constructed of a simple logic circuit, for instance.
A modified conventional scanning electrode means (a Y shift register) may be used as the write timing means of the present invention. Specifically, employed as the write timing means are odd-frame scanning electrode drive means for successively generating the first write timing signal for rows of pixels during the odd frame period through the first scanning electrodes, and even-frame scanning electrode drive means for successively generating the second write timing signal for rows of pixels during the even frame period through the second scanning electrodes.
The above-referenced pixel drive means includes first signal reading means for reading a first temporary storage signal by on and off operations in response to a first read timing signal, second signal reading means for reading a second temporary storage signal by on and off operations in response to a second read timing signal, and common pixel drive means for performing pixel driving on the pixel electrodes in response to the signal that is successively read from the first signal reading means and the second signal reading means. The pixel drive means separately performs the read-only function and the pixel drive-only function. The pixel drive means may be used for digital driving and analog driving.
When the prior signal is read from the first signal hold means through the first signal reading means, the common pixel drive means drives the pixel electrodes for one frame period in response to the prior signal. When the subsequent signal is read from the second signal hold means through the second signal reading means in the next frame period, the common pixel drive means drives the pixel electrodes in response to the subsequent signal.
The first signal reading means is a third transistor with one terminal thereof electrically connected to the first sample-and-hold means and with the other terminal thereof electrically connected to a control input of the common pixel drive means. The second signal reading means is a fourth transistor which is of the same semiconductor type as that of the third transistor, with one terminal thereof electrically connected to the second sample-and-hold means and with the other terminal thereof electrically connected to the control input of the common pixel drive means. The use of the third and fourth transistors of the same semiconductor type controls differences in element characteristics, thereby providing advantages in analog driving. Since the two transistors perform on and off operations in accordance with on and off control signal of the same logic, the two transistors need their own dedicated scanning electrodes for exclusive on and off control.
In contrast, the first signal reading means may be a third transistor with one terminal thereof electrically connected to the first sample-and-hold means and with the other terminal thereof electrically connected to a control input of the common pixel drive means. The second signal reading means may be a fourth transistor which is of a semiconductor type complementary to that of the third transistor, with one terminal thereof electrically connected to the second sample-and-hold means and with the other terminal thereof electrically connected to the control input of the common pixel drive means. The two transistors are thus complementary to each other in polarity. In such a case, the third and fourth transistors respectively perform the on and off operations in accordance with mutually opposite logic on and off control signals, and a single common scanning electrode for the write timing signal works.
The common pixel drive means may be a fifth transistor with one terminal thereof electrically connected to a pixel drive power source and with the other terminal thereof electrically connected to the pixel electrode.
Another pixel drive means may include first pixel drive means for reading a first temporary storage signal by on and off operations in response to a first read timing signal and performing pixel driving on the pixel electrode in accordance with the read signal, and second pixel drive means for reading a second temporary storage signal by on and off operations in response to a second read timing signal and performing pixel driving on the pixel electrode in accordance with the read signal. The pixel drive means separately performs prior signal only reading and driving function and subsequent signal only reading and driving function. The pixel drive means is particularly suitable for use in analog driving.
When the prior signal is read from the first signal hold means through the first pixel drive means, the pixel electrodes are driven during one frame period in response to the prior signal. When the subsequent signal is read from the second signal hold means through the second pixel drive means during the next frame period, the pixel electrodes are driven during one frame in response to the subsequent signal. With no common pixel drive means incorporated, the active element count in the active element circuit and the lines for the pixel drive power source are accordingly reduced.
Like the above-referenced first pixel exciting means, in this pixel drive means, the first pixel drive means is a third transistor with one terminal thereof electrically connected to the first sample-and-hold means and with the other terminal thereof electrically connected to the signal electrode. The second pixel drive means is a fourth transistor which is of the same semiconductor type as that of the third transistor, with one terminal thereof electrically connected to the second sample-and-hold means and with the other terminal thereof electrically connected to the pixel electrode. The use of the third and fourth transistors of the same semiconductor type controls differences in element characteristics, thereby providing advantages in analog driving.
With these pixel drive means incorporated in the active element circuit, read timing means is required in the peripheral circuits to generate the first read timing signal and the second read timing signal. Taking advantage of a timing signal that alternates each frame period, the read timing means may generate the first read timing signal during the odd frame and the second read timing signal during the even frame.
When the first read timing signal and the second read timing signal are alternately generated every frame period in an exclusive manner, there is a possibility that one or both of the first signal reading means (the first pixel drive means) and the second signal reading means (the second pixel drive means) become conductive at the frame switching, making a hold signal irregular. The read timing means is preferably read idle timing means which interposes a blanking period between the first read timing signal and the second read timing signal. The read idle timing means may be constructed of a simple logic circuit that uses the AC driving signal and a blanking period setting clock. In the color sequential type display, in particular, an additive color process is prevented during the color light source switching, and a high color image quality results.
The first pixel drive means is a third transistor with one terminal thereof electrically connected to the first sample-and-hold means and with the other terminal thereof electrically connected to the signal electrode. The second pixel drive means is a fourth transistor which is of a semiconductor type complementary to that of the third transistor, with one terminal thereof electrically connected to the second sample-and-hold means and with the other terminal thereof electrically connected to the pixel electrode. In this arrangement, the first read timing signal and the second read timing signal are opposite to each other in logic. Even if the first read timing signal and the second read timing signal are alternately generated in an exclusive manner, the possibility of concurrent conduction of the transistors at the frame switching is low, compared to the same semiconductor type transistors. The timing signal that alternates every frame is used as the first read timing signal during the odd frame and is used as the second read timing signal during the even frame. This arrangement serves the purpose of simplification of the peripheral circuit. Even in this case, however, the setting of a blanking period prevents the additive color process during the color light source switching in the color sequential type display, and a high color image quality results.
The substrate for the electrooptical device of the present invention is not limited to the one in which the above-discussed active element circuit is embedded in a monocrystal semiconductor substrate. The substrate may be one in which a TFT is formed on an insulating transparent substrate, such as a glass substrate or a quartz substrate, using thin-film technique. Compared to the above-described active element circuit, such substrate finds many applications as a transparent electrooptical device substrate, although it has a slightly higher component count.
When the signal on the signal line is an analog signal, analog driving is performed on the pixels. When the signal on the signal line is pulse-width modulated, digital driving is performed on the pixels.
An electrooptical device is constructed by assembling the above-referenced electrooptical device substrate and an opposing transparent substrate, and by encapsulating an electrooptical material between the substrates. The electrooptical material is not limited to a liquid crystal. Alternatively, a new electrooptical material for a voltage-driven element, such as an EL (Electroluminescence) material or DMD (digital mirror device) material, may be employed.
When a common voltage that alternates every frame period is applied, directly or via the electrooptical device substrate, to the opposing electrode of the transparent substrate in the electrooptical device, the electrooptical material is AC driven even if the AC driving of the pixel electrode is difficult. For instance, when the electrooptical material is a liquid crystal, a degradation of the liquid crystal is avoided. Since the dynamic range of the signal applied to the pixel electrode is relatively reduced, active elements in the active element circuit are fabricated of low withstand-voltage ones. This permits fine structured elements to be implemented, leading to a reduced area size of the element. A high-definition display apparatus with an increased aperture ratio thus results.
When such an electrooptical device is incorporated in a diversity of electronic equipment as a display unit, a high image quality display is presented. The electrooptical device is appropriate for use as a light valve in a projection display apparatus, for instance.
To resolve the problems, the present invention provides first means in a substrate for an electrooptical device (digitally driven display device such as LC, DMD, FED, PDP, EL, or LED) including a pixel electrode for each of pixels arranged at intersections of scanning electrodes and signal electrodes in a matrix configuration,. wherein each pixel is associated with digital storage means which performs concurrently in parallel both a pixel driving operation in accordance with temporarily stored prior digital data (data of a prior frame, for instance) and a temporary storage operation for subsequent digital data (data of a subsequent frame, for instance) of the same pixel that comes in to the signal electrode after a constant duration from the prior digital data.
In conventional active element circuits, the timing of temporarily storing data in a storage capacitor and the timing of pixel driving the electrooptical material with the same data coincide with each other. In accordance with the electrooptical device substrate of the present invention, the timing of temporarily storing the data from the signal electrode and the timing of reading the temporarily stored signal to drive the pixel are positively phase-shifted until all pixel data are accumulated. Data is written on all pixels during the prior frame period, and all pixels are concurrently displayed (in a still image) during the next frame period. The constant duration is not limited to a full frame period, and when one full frame successively includes R, G, and B subframes in a color-sequential display method (a field color successive presentation method), the subframe is also treated as a constant duration.
Regardless of the point-at-a-time scanning method or the line-at-a-time scanning method, the write sequence is merely a temporary storage sequence in the present invention. The write sequence is not pronounced as a pixel drive sequence, and frame switching is performed at a time on all pixels. For this reason, the non-uniformity on the display screen is eliminated, and a substrate for an electrooptical device having a high image quality is provided. A large-size display screen or high-definition display screen results regardless of the number of pixels. Since the ratio of the display time and the write time within one frame period are not exclusive to each other, the display time for all pixels is allowed to be longer than that in the conventional art, and a higher definition display is thus provided. The write operation for all pixels throughout a predetermined period of time (one frame period, for instance) is performed, allowing the write time to be extended. With a slow signal transfer speed, the peripheral circuits are simplified in construction or modified to accommodate a higher number of pixels. A frame memory for display data attached external to the electrooptical device substrate is dispensed with.
When the signal on the signal electrode is pulse-width-modulated, the digital driving of the pixel is possible. In the present invention, however, the pixel driving method is a static driving based on temporarily stored data rather than a dynamic driving, and is thus free from the attenuation of a pixel drive signal. A perfect digital driving is thus possible.
When a plurality of storage cells are connected in parallel and operative with the signal electrode in an exclusive or alternate manner in the first means, the storage cells need to be switched at the switching of the frames. Driving the pixel electrodes constantly in a static driving manner using the same storage cells is difficult.
The present invention thus provides second means in an electrooptical device substrate including a pixel electrode for each of pixels arranged at intersections of scanning electrodes and signal electrodes in a matrix configuration, wherein each pixel is associated with digital storage means which successively shifts digital data coming to the signal electrode along a plurality of cascaded storage cells while temporarily storing the digital data and drives the pixels in accordance with an storage output of the last stage of the storage cells.
Since in such digital storage means, the last stage of the storage cells is the one responsible for static driving of the pixel electrode, perfect digital driving becomes possible. It is generally sufficient if two stages of storage cells are used. The use of three or more stages of storage cells is optional. When the storage cells are of two stages, the construction thereof becomes delay means with a phase shift quantity having a predetermined duration, and is identical to a shift register or an FIR filter having one or more taps.
When the two-stage storage cells are used, the digital storage means includes first latch means for capturing and temporarily storing digital data coming to the signal electrode, and second latch means for reading and temporarily storing prior digital data, which the first latch means stored a constant duration prior to the digital data, before the data capturing by the first latch means, and for driving the pixels in response to the storage output thereof. The digital storage means is characterized in that the second latch means performs static driving while the first latch means functions as data delay means.
The first latch means includes first data selecting means for capturing the digital data, and a first flipflop for temporarily storing the data captured by the first data selecting means. The second latch means includes second data selecting means for capturing the output data from the first flipflop, and a second flipflop for temporarily storing the data captured by the second data selecting means. The storage output of the second flipflop is electrically connected to the pixel electrode. The first flipflop functions as data delay means, while the second flipflop functions as static drive means for the pixel electrode.
The data selecting means may be arranged in a variety of configurations. For instance, the first data selecting means may be a first data-transfer transistor that becomes conductive in synchronization with a first timing pulse, the first flip flop may be a first synchronization flipflop that performs a storage operation in synchronization with the first timing pulse, the second data selecting means may be a second data-transfer MOSFET that conducts in synchronization with a second timing pulse that is generated prior to the second timing pulse, and the second flipflop may be a second synchronization flipflop that performs a storage operation in synchronization with the second timing pulse. The use of the data selecting means, fabricated of a single transistor, serves the purpose of component count reduction.
Alternatively, the first data selecting means may be a first one-input gating element that performs a logic operation in synchronization with the first timing pulse, the first flipflop may be a first synchronization flipflop that performs a storage operation in synchronization with the first timing pulse, the second data selecting means may be a second one-input type gating element that performs a logic operation in synchronization with the second timing pulse, and the second flipflop may be a second synchronization flipflop that performs a storage operation in synchronization with the second timing pulse. Although the one-input gating element requires two or more transistors, this arrangement is effective in the reduction of power consumption, wave shaping, and energy amplification, functions as writing and drive means, and helps assure that storage operation be reliably performed. The one-input type gating element may be a clocked inverter or a three-state buffer.
The flipflop may be arranged in a variety of configurations. For instance, the first synchronization flipflop includes a first even-number inverter circuit having an even number of inverters connected in a cascade configuration, and a first storage control transistor for temporarily disconnecting an electrical connection between the input of an initial-stage inverter and the output of a feedback-stage inverter in synchronization with the first timing pulse. The second synchronization flipflop includes a second even-number inverter circuit having an even number of inverters connected in a cascade configuration, and a second storage control transistor for temporarily disconnecting an electrical connection between the input of an initial-stage inverter and the output of a feedback-stage inverter in synchronization with the second timing pulse.
When a logic value, different from a logic value stored in the even-number inverter circuit, is set through the data selecting means with the output of a feedback-stage inverter connected to the input of the even-number inverter circuit, the set logic value and the storage logic value interfere with each other, causing an unstable state. During the setting of the even-number inverter circuit, the storage operation is temporarily suspended by the storage control transistor so that the setting of data from the data selecting means is prioritized. After the data setting, the storage control transistor is turned on, performing data storage.
The first synchronization flipflop is a first even-number inverter circuit having an even number of inverters connected in a cascade configuration, with a feedback stage inverter thereof being a clocked inverter which suspends a logic operation in synchronization with the first timing signal. The second synchronization flipflop is a second even-number inverter circuit having an even number of inverters connected in a cascade configuration, with a feedback stage inverter thereof being a first clocked inverter which suspends a logic operation in synchronization with the second timing signal. In this case again, the storage operation is suspended by the clocked inverter during the setting so that the setting of data from the data selecting means is prioritized.
Although the even-number inverter circuit having a large number of stages provides a stronger buffer effect, a double inverter circuit having two stages of inverters suffices. This arrangement reduces the component count.
The substrate of the electrooptical device of the present invention includes a peripheral drive circuit including a serial-to-parallel converting shift register for applying the digital data to the signal electrode, a scanning electrode selecting shift register for successively selecting the scanning electrodes, and latch timing means for generating the first timing signal in accordance with a scanning electrode drive wave from the scanning electrode selecting shift register. The implementation of a high degree of integration results in a cost reduction.
The substrate for the electrooptical device of the present invention is not limited to the one in which the above-discussed digital storage means is embedded in a monocrystal semiconductor substrate. The substrate may be one in which a TFT is formed on an insulating transparent substrate, such as a glass substrate or a quartz substrate, using thin-film technique. Although the substrate of the electrooptical device of the present invention has a slightly higher component count, compared to the above-described active element circuit, the aperture ratio thereof is not a problem in a projection display apparatus. The use of fine structure technique in the element areas allows the substrate of the present invention to find applications as a transmissive electrooptical device substrate.
An electrooptical device is constructed by assembling the above-referenced electrooptical device substrate and an opposing transparent substrate, and by encapsulating an electrooptical material between the substrates. The electrooptical material is not limited to a liquid crystal. Alternatively, a new electrooptical material for a voltage-driven element, such as an EL (Electroluminescence) material or DMD (digital mirror device) material, may be employed.
When a common voltage that alternates every frame period (a frame period, for instance) is applied, directly or via the electrooptical device substrate, to the opposing electrode of the transparent substrate in the electrooptical device, the electrooptical material is AC driven even if the AC driving of the pixel electrode is difficult. For instance, when the electrooptical material is a liquid crystal, a degradation of the liquid crystal is avoided. Since the logical amplitude of the signal applied to the pixel electrode is relatively reduced, active elements in the active element circuit can thus be fabricated of low withstand-voltage ones. This permits fine structured elements to be implemented, leading to a reduced area size of the element. A high-definition display apparatus with an increased aperture ratio thus results.
When such an electrooptical device is incorporated in a diversity of electronic equipment as a display unit, a high image quality display is presented. The electrooptical device is appropriate for use as a light valve in a projection display apparatus, for instance.